The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Semiconductor memory (memory) packaged in integrated circuits (ICs) is typically organized in the form of memory arrays. Memory arrays that comprise NAND-type or NOR-type memory cells (e.g., NAND-type or NOR-type Flash memory cells) are called NAND-type or NOR-type memory arrays, respectively. Memory arrays comprise memory cells arranged in rows and columns. Memory arrays comprise decoder circuits (decoders) that select word lines (WLs) and bit lines (BLs) to read/write data in the memory cells.
Referring now to FIG. 1, an IC 10 comprising a memory array 12, a WL decoder 16, and a BL decoder 18 is shown. The memory array 12 comprises memory cells 14 arranged in rows and columns as shown. During read/write operations, depending on the address of a selected memory cell 14, the WL and BL decoders 16, 18 activate appropriate WLs and BLs, respectively, to read/write data from/to the selected memory cell 14.
Referring now to FIG. 2, an exemplary NOR-type memory array 50 utilizing a buried bit line architecture is shown. A state of an nth memory cell 52 in the NOR-type memory array 50 is typically measured as follows. A WL decoder 51 selects a word line WL(n) and deselects a word line WL(n+1). A sensing circuit 54 applies a potential difference (V2−V1) across adjacent bit lines BL(n) and BL(n+1) that connect directly to the nth memory cell 52. The sensing circuit 54 senses and measures a current I that flows through the nth memory cell 52. A value of the current I depends on the state of the nth memory cell 52. The state of the nth memory cell 52 can be determined based on the value of the current I.
Typically, a pair of decoders may be used to select different pairs of adjacent bit lines that connect to different memory cells of memory arrays. The decoders may apply the potential difference (V2−V1) across the selected pairs, measure the current that flows through the selected memory cells, and determine the state of the memory cells.
Referring now to FIG. 3, an exemplary integrated circuit 70 comprising a NOR-type memory array 72, a WL decoder 74, a decoder 76, a decoder 78, and a sensing circuit 80 is shown. The decoders 76 and 78 are 1-of-N decoders, where N is an integer greater than 1 (e.g., N=8). The decoders 76 and 78 select different pairs of adjacent bit lines that connect to different memory cells of the NOR-type memory array 72. The decoders 76 and 78 apply the potential difference (V2−V1) across the memory cells connected to the selected bit lines. The sensing circuit 80 measures the current that flows through the memory cells. Thus, states of all the memory cells of the NOR-type memory array 72 can be determined.